PUSCH Equalizer for 3GPP 5G NR
3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel sol…
- Channel Coding
- 3GPP 5G NR
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
PUSCH Equalizer for 3GPP 5G NR
3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel sol…
Run-time Reconfigurable Neural Network IP
The Dynamic Neural Accelerator II (DNA-II) is a -efficient and neural network IP core that can be paired with any host processor.
100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm wit…
Neural engine IP - Tiny and Mighty
Small, low-power dedicated AI engines are essential for home appliances, security cameras, and always-on smartphone features.
CCSDS 231.0 LDPC(128, 64) and LDPC(512, 256) Encoder and Decoder
The IPrium-LDPC-CCSDS-231-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm f…
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…
Low-power high-speed reconfigurable processor to accelerate AI everywhere.
Zhufeng-800: A low-power high-speed reconfigurable processor to accelerate AI everywhere.
Even the smallest, lowest-power audio devices embed AI capabilities to enhance the user experience.
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
Scalable Edge NPU IP for Generative AI
Ceva-NeuPro-M is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, …
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
KJN-S1 is able to get Higher performance lossless Compression by original algorithm.
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, …
LDPC corrects errors caused by flash storage failure mechanisms.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
Designed to enable low power signal conditioning for IoT edge endpoints.
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specifi…