Original Lossless codec IP core - Full HD 30fps@126MHz (1 Sample/clk)
KJN-S1 is able to get Higher performance lossless Compression by original algorithm.
Overview
KJN-S1 is able to get Higher performance lossless Compression by original algorithm.
Key features
- Lossless compression/decompression specification of Shikino-High Tech original algorithm.
- The core get Highest Compression and Smallest circuit by we have grown up compression/decompression algorithm
- Available of loading both ASIC and FPGA.
- Image in/output format:pixel interleave
- Image size : arbitrary
- Operation mode like processing mode, image size etc. are set in internal register via external CPU.
- Written from external during compression, and downloaded from compressed data during decompression.
- Marker : Automatically generated on Encode, and automatically analyzed on Decode.
- DLL for compression / decompression provided (windows version)
Block Diagram
Applications
- Smart phone
- Digital still cameras
- Broadcast equipment
- Medical equipment
- info input/output system
- Monitoring system
- Aerospace image system
- image data transfer unit
- Image transfer devices
What’s Included?
- RTL:Verilog-HDL
- C-Model
- Specification Document
- Simulation environment
- Synthesis scripts
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Data Compression IP core
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Frequently asked questions about Data Compression IP
What is Original Lossless codec IP core - Full HD 30fps@126MHz (1 Sample/clk)?
Original Lossless codec IP core - Full HD 30fps@126MHz (1 Sample/clk) is a Data Compression IP core from Shikino High-Tech CO.,LTD listed on Semi IP Hub.
How should engineers evaluate this Data Compression?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.