Run-time Reconfigurable Neural Network IP

The Dynamic Neural Accelerator II (DNA-II) is a highly-efficient and powerful neural network IP core that can be paired with any host processor. Achieving exceptional parallelism and efficiency through run-time reconfigurable interconnects between compute elements, DNA-II has support for both convolutional and transformer networks, and is ideal for a wide variety of edge AI applications. DNA-II provides scalable performance starting with 1K MACs supporting a wide range of target applications and SoC implementations.

The MERA software stack works in conjunction with DNA to optimize computation order and resource allocation in scheduling tasks for neural networks.

DNA is the driving force behind the SAKURA-II AI Accelerator, providing best-in-class processing at the edge in a small form factor package, and supporting the latest models for Generative AI applications.

DNA-II Efficiency

Tera Operations Per Second (TOPS) ratings are typically quoted using optimal conditions, with compute units fully parallelized. When AI models are mapped to other vendors hardware, the parallelism drops - and achievable TOPS falls to a fraction of their claimed peak capability.

EdgeCortix reconfigures data paths between DNA engines to achieve better parallelism and reduce on-chip memory bandwidth, using a patented runtime reconfigurable datapath architecture.

• Customizable IP Implementation: Achieve desired performance (TOPS), size, and power for target implementation and process technology
• Optimized for Generative AI: Supports popular Generative AI models including LLMs and LVMs
• Efficient AI Compute: Achieves very high AI compute utilization, resulting in exceptional energy efficiency
• Real-Time Data Streaming: Optimized for low-latency operations with batch=1
• Arbitrary Activation Function Support: Hardware accelerated approximation provides enhanced adaptability
• Advanced Precision: Software-enabled mixed-precision provides near FP32 accuracy
• Efficient Memory Utilization: Reduces memory footprint and optimizes DRAM bandwidth, using efficient memory compression
• Power Management: Advanced power management enables ultra-high efficiency modes. DNA Cores can be optimized for power/performance trade-offs
• Flexible Compute Blocks: Compute block uses optimized systolic arrays from 32x32 to 64x64 elements. Separate vector unit powers neural network activation and scaling
• Optional Reshaper IP: Integrated tensor reshaper engine minimizes host CPU load

• Run-time reconfigurable
• Efficient AI inference core in FPGAs or SoCs
• Low latency
• < 4 msec when under demanding workloads
• High utilization
• +80% for concurrent neural network models

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