LDPC Decoder for 5G NR and Wireless
The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal p…
- Channel Coding
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
LDPC Decoder for 5G NR and Wireless
The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal p…
32 Bit - Embedded RISC-V Processor Core
Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.
DVB-S2X Wideband LDPC/ BCH Decoder
The DVB-S2X Wideband LDPC Decoder is a FEC core decoder for Digital Video Broadcasting via Satellite.
Introducing Gyrus's ground-breaking AI Processor Accelerator IP, coupled with a native graph processing software stack, is the ul…
High performance FFT with Gsps throughput
The eSi-FFT-Gsps is an FFT design tailored for high-throughput applications, specifically design to seamlessly integrate with hig…
The D68000-CPU32+ soft core is binary-compatible with the industry standard 68000’s CPU32+ version of the 32-bit microcontroller.
Reed Solomon Encoder and Decoder
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
Performance AI Accelerator for Edge Computing
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture an…
Performance Efficiency AI Accelerator
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture an…
Lowest Power and Cost End Point AI Accelerator
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture an…
Highly scalable performance for classic and generative on-device and edge AI solutions
Scalable and Power-Efficient Neural Processing Units The Neo NPUs offer energy-efficient hardware-based AI engines that can be pa…
NR-5G Polar Decoder and Encoder
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a FEC code is…
Wide range of dedicated, high performance, low latency RS FEC IP cores to meet any error correction requirement The Reed Solomon …
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
The IPrium-SOQPSK-LDPC-Modulator IP Core implements constant amplitude CPM SOQPSK modulation with LDPC Coding.
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their …
Vision DSP built using 128-bit SIMD and offering up to 0.4 TOPS of performance
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Cache-Coherent HiFi 5s Symmetric Multiprocessor
Efficient 32-bit processing for audio enhancement algorithms, wideband voice codecs, and multi-channel audio The Cadence® Tensili…
Efficiently supports front-end audio processing like beamforming and noise reduction, as well as neural network-assisted speech r…