Vendor: Global IP Core Sales Category: Channel Coding

MIMO MMSE Decoder

The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.

Overview

The MIMO Decoder accepts two independent input streams, and the channel estimation matrix. The inputs to the MIMO Decoder are the estimated channel matrix and the received vector of symbols. Since the transmitted symbols could be pre-coded, some processing may be needed (optional) at the beginning of the detection. The QR decomposition is performed in preparation for the K-Best decoding. The outputs of the QR decomposition are fed to the K-Best decoder.
 

Key features

  • Includes QR Decomposition, Dynamic scale and K-best Decoder
  • Fixed Depth K-Best Decoder (K=16)
  • Achieves close-to ML BER performance
  • Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
  • Supports square and non-square QAM
  • Supports OFDM based systems with different Space Time Coding (STC)
  • Soft input soft output
  • Supports ( MIMO 2X2) or (MIMO 3X3) or (MIMO 4X4), selectable during run time

Applications

  • MIMO systems
  • Wi-Fi IEEE 802.11n/ac
  • WiMAX 802.16e
  • LTE standard
  • RFID
  • DVB-NGH

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab)
  • Verilog Test Benches
  • Documentation

Specifications

Identity

Part Number
MIMO MMSE Decoder
Vendor
Global IP Core Sales
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Channel Coding IP cores

What is MIMO MMSE Decoder?

MIMO MMSE Decoder is a Channel Coding IP core from Global IP Core Sales listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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