Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Latest Energy Vision DSP targeting low-end Vision/Radar and AI SOC market
The Cadence Tensilica Vision 110 DSP is the latest addition to the Vision DSP family. The smallest Vision DSP targets lower power, always-on applications offering one-third the power and area compared to the 512-bit SIMD Vision 130 DSP, while offering an easy software transition from Vision 110 via the N way programming model, and previous generation Vision P1 DSP. Vision 110 DSP also offers the flexibility to configure without various features to reduce area and the data RAM.
Cadence, through its Tensilica processor IP, brings together best-in-class products and services from industry leaders to help you accelerate the development of your SoC designs while meeting your demanding power and performance requirements. Browse the list of Tensilica processor IP service partners below.
Area and Power Optimized
128-bit SIMD with lowest area and power among the Vision DSPs and lower power compared to host CPU and GPU
Vision/Image Processing
Instructions set optimized for computer vision and image processing applications
High Performance
> 0.256TOPS AI performance for object detection, image classification, Image segmentation
Note: some files may require an NDA depending on provider policy.
Vision DSP built using 128-bit SIMD and offering up to 0.4 TOPS of performance is a DSP Core IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.