Overview
Advanced 3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel solution
AccelerComm’s PUSCH Equaliser IP product offers a complete high-performance 3GPP compliant PUSCH channel for a gNB, bringing on average 29% savings in infrastructure power and equipment cost for typical private networks and $193M increase in Net Present Value for typical Fixed-Wireless Access networks.
MIMO equalisation
MIMO equalisation is fundamental in 5G NR to tackle co-channel interference imposed by multiple transmissions in the time, frequency and space domains, to achieve ever higher spectral efficiency and reduce cost per bit for 5G applications in sub 6GHz and mmWave. To hit a ‘sweet spot’ between computational complexity and spectral efficiency, many challenges must be overcome. AccelerComm has introduced advanced 5G NR MIMO equalisation techniques based on state-of-the-art algorithms such as MMSE-IRC, to enable higher spectral efficiencies at both low and high SNRs. Delivering a 3dB improvement in uplink receive sensitivity for a deployed gNodeB solution, these techniques can be deployed in 5G small cell, macro cell and satellite applications.
Integrating and validating the whole set of signal processing tasks of the Physical Uplink Shared Channel (PUSCH) channel requires a significant investment in engineering resource. Trusted by Tier-1 technology companies and leading semiconductor companies with our 5G NR IP, AccelerComm has built up a strong product portfolio and expertise in the field of the L1 physical layer. With LDPC, Polar, PDSCH Encoder, PUSCH Decoder and now PUSCH equaliser (MIMO equalisation), AccelerComm’s latest IP product offers benefits of UCI over PUSCH and improved throughput and dB gain for the PUSCH channel, while greatly reducing the risks and providing market-leading solutions and faster time to market for FPGA and ASIC 5G platforms.
Learn more about Channel Coding IP core
One question we get asked by most of our customers when they are designing our technology into their systems is what is the processing throughput? It turns out that the answer to this question is a little more complex than you might think. It’s tempting to simply state the peak throughput of the component in question, but that can sometimes be quite misleading.
This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.
We describe our SoC implementation of a baseband subsystem for a high performance 4G terminal. Our architecture, called FAUST, is based on distributed synchronization and asynchronous communication. We highlight how we have actually implemented these two
Satellite modems structure Internet access
DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.
