Nonbinary LDPC Decoder
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
Overview
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are a powerful family of FEC codes that allow for very low error rates, approaching the Shannon capacity limit.
While binary LDPC codes have shown great performance, nonbinary LDPC codes have empirically shown even better performance, especially for small codeword lengths.
A configurable output synchronous FIFO is used to store the output for the next block.
Key features
- Regular parity check matrix
- Soft decision SPA decoding
- Supports different code sizes
- Hard decision output
- Log-domain implementation
- Configurable number of decoding iterations
- Higher-order Galois field GF(2m)
Applications
- Real-time applications
- Short codeword length applications
- BeiDou Navigation Satellite System
What’s Included?
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is Nonbinary LDPC Decoder?
Nonbinary LDPC Decoder is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.