Overview
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. A pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output.
AR4JA LDPC decoder uses a Min-Sum algorithm to perform decoding. The min-Sum algorithm is an iterative algorithm that progresses to convergence through two updates: check node update and variable node update. Check node update is evaluated by calculating the minimums and signs of all connected variable nodes. Then variable node update takes place. Processing is done layer by layer until all layers and iterations are completed.
Learn more about Channel Coding IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
