DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…
Overview
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1 .4 specification. It contains additional safety features to detect and report transient or permanent faults in order to meet the high level of safety required by automotive applications. The IP core is ASIL-B ready, as per the ISO 26262 standard.
ASIL-B certified solution for automotive applications
Key features
- VESA DisplayPort 1.4 compliant
- Reed-Solomon RS (254,250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
- DisplayPort main 8b/10b encoder included (Tx only)
- Status and control can be done with signals or optionally via an integrated APB register module (Rx)
- Single unified APB interface supports 4-lane mode (Rx)
- Performance monitoring and statistics counters (Rx)
Block Diagram
Applications
- Automotive GPUs
- Infotainment systems
- DisplayPort 1.4 automotive products
- USB-C automotive products
What’s Included?
- Encrypted RTL source code IP core
- Functional and structural coverage reports
- Comprehensive integration guide
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B?
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B is a Channel Coding IP core from Rambus, Inc. listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.