64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
- RISC-V
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
64-bit High performance Quad Core RISC-V Microprocessor
VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Dual Core Microprocessor
VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirement…
64-bit High performance Single Core Microprocessor
VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requir…
64-bit RISC-V Single Core Microprocessor
VEGA AS1061 features an in-order processing engine with a 6 stage pipeline enabling it to meet high-performance embedded applicat…
32-bit RISC-V High Performance Microcontroller Class Processor
VEGA ET1031 is a compact 3-stage in-order 32-bit RISC-V processor core ideal for low power applications.
IP platform for intelligence gathering chips at the Edge
Designed to be the solution for an AI compute device right at the Edge, Sondrel’s new SFA 100 IP reference platform makes creatin…
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with…
DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
The is a single-chip DVB-T, T2, C, S and S2 demodulator IP core extratced from production chip and silicon proven IP core.
SFA 300 is designed to implement scalable processing applications supporting local networking.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000’s CPU32 version of the 32-bit microcontroller.
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizab…
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructi…
Highest performance real-time processor
Highest-performance Cortex-R processor with memory management unit (MMU), enabling real-time and rich operating systems (OS), suc…
High performance Linux-capable processor
The SiFive U84 Standard Core is a single-core instantiation of our most scalable out-of-order RISC-V application processor, and i…
Radar processing IP suite for Advanced Driver Assistance Systems
The eSi-ADAS™ is a suite of radar accelerator IP including a Radar co-processor engine, they enhance the overall performance and …
Kalman Filter hardware accelerator
The eSi-Kalman core provides hardware acceleration for Kalman Filtering (KF) and related target tracking algorithms, such as meas…
High performance FFT optimised for Radar
A configurable efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generati…
Ceva-SensPro is a family of DSP cores architected to combine vision, Radar, and AI processing in a single architecture.