Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Gigabit-range, low complexity LDPC decoder
TC4902 is ideally suited for applications requiring a very efficient throughput/area ratio, while not sacrificing SNR performance.
Error Correction Checking (ECC) Core
The Xilinx LogiCORE™ IP ECC core is ideal for robust data transmission with error correction and checking capabilities.
Xilinx provides a generic forward error correction (FEC) engine to generate and insert a SMPTE ST2022 compliant video over IP FEC…
The Backhaul Low Density Parity Check (LDPC) core IP provides a high-performance forward error correction (FEC) solution for mobi…
Flash Memory LDPC Error Correction
The Xilinx® LogiCORE™ IP Flash Memory low-density parity-check (LDPC) Error Correction core is a major component for improving fl…
The CMS0069 DVB-CID Modulator provides all the necessary processing steps to modulate the Content-ID table into a complex I/Q sig…
EdgeQAM IP Core Set (1 x RF Port, 160-Ch, ADI)
Developed in collaboration with Xilinx®, Inc., the RADX™ EdgeQAM IP Core Set is a modular, scalable set of Intellectual Property …
LDPC Decoder and Encoder that supports DVB-S2 DVB-S2X DVB-T2 DVB-C2 CMMB DMB-T
LDPC Decoder and Encoder that supports DVB-S2 DVB-S2X DVB-T2 DVB-C2 CMMB DMB-T
The 3GPP Mixed Mode Turbo Decoder provides a flexible turbo convolutional decode function for both LTE and UMTS air interfaces.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
The Zaltys DVB-S2 Modulator (DVBS2-M) IP core is a variant of the Zaltys HDRM-M Modulator core which implements a DVB-S2 complian…
The Zaltys DVB-S2 Demodulator (DVBS2-D) IP core is a variant of the Zaltys HDRM-D2 demodulator core which implements a DVB-S2 com…
The Zaltys High Data Rate Modulator (HDRM-M) IP core efficiently realizes the digital baseband section of a high performance mode…
High Data Rate Enhanced Demodulator
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
DVB-S demodulator / DSNG demodulator
The CMS0048 DVB-S/DSNG Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S and DVB DSNG forward link app…
The CMS0059 Satellite Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S, DVB-DSNG, DVB-S2 and DVB S2X …
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
Xilinx provides a market DPD solution that reduces CapEx and OpEx Digital Pre-Distortion (DPD) is one of the most fundamental bui…
The 3GPP LTE Channel Estimator LogiCORE™ IP provides an optimized channel estimation function for the Physical Uplink Shared Chan…
The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matric…