A Finite Impulse Response (FIR) filter performs a convolution of an input data sequence with the filter's impulse response (the d…
- Filters Transforms
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
A Finite Impulse Response (FIR) filter performs a convolution of an input data sequence with the filter's impulse response (the d…
The Divider IP core is a one-clock divider which completes one integer division every clock.
Lattice DFE (Digital Front End) demo provides a digital solution consisting of CPRI (Common Public Radio Interface), DUC (Digital…
Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used …
Convolutional encoding is a process of adding redundancy to a signal stream.
FFT - Streaming Mixed-Radix Architecture
The FFT/IFFT IP core is a configurable Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) VHDL IP component.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
50G IEEE 802.3 Reed-Solomon Forward Error Correction
Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) subl…
IEEE 802.3bj Reed-Solomon Forward Error Correction
Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise…
The Reed-Solomon Forward Error Correction (RS-FEC) IP Solution implements the RS-FEC sublayer specified in IEEE 802.3by/D3.1.
The Forward Error Correction (FEC) IP core is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 1…
24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter
The ASRC-pro (CWda52) is part of Coreworks family of multi-channel Asynchronous Audio Sample Rate Converters (ASRC).
16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter
The ASRC-lite (CWda50) is part of Coreworks family of multi-channel asynchronous Audio Sample Rate Converter (ASRC).
hellaPHY™ RSTD IP core addresses new FCC E911 indoor location accuracy requirements, and opens the door for low-cost IoT wireless…
TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications.