Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
- GlobalFoundries
- 130nm
- RFSOI
- Silicon Proven
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 3bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 4bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 4bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 2bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 2bit - GlobalFoundries 130nm RFSOI
RF Counter, 8b - GlobalFoundries 40nm
RF Counter, 8b - GlobalFoundries 40nm
RF Counter, 16b - GlobalFoundries 55nm
RF Counter, 16b - GlobalFoundries 55nm
Soft-Decision FEC Integrated Block
For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is …
The Polar Encoder/Decoder soft IP core supports Polar encoding and decoding.
Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…
The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
25G IEEE 802.3by Reed-Solomon Forward Error Correction
Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise …
Narrow band - IoT Release-14 UE PHY. (L1) IP
This NB-IoT PHY.
Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolu…
Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used …
FFT - Streaming Mixed-Radix Architecture
The FFT/IFFT IP core is a configurable Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) VHDL IP component.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.