Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the several variants of the Majority Voting combination rule to calculate the ensemb…
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords.
1KB/ECC96 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
The Zaltys ISDBT-M IP core is a 3-layer ISDB-T hierarchical modulator compatible with the ARIB STD-B31 standard for Terrestrial I…
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications.
512B/ECC16 Nand Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
High-performance Low-memory Mixed Radix FFT
This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT.
1KB/ECC40 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
High Performance DTMB (GB20600-2006) Demodulator Core
Digital demodulator fully supporting GB20600-2006 China DTV standard.
The TC4500 Core complies with DVB-T2 specifications.
TC1700 is a FEC receiver adressing LTE, LTE-A, WiMAX, HSPA/+, and legacy 3G standard.
3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories
This is a fully compatible 3GPPTM LTE and 3GPP2 1xEV-DO Release B turbo decoder with ping-pong input and output memories.
The MW_DVB-T/H modulator core performs the digital baseband function for the transmission side of Digital Video Broadcasting Terr…
The MW_DVBS2 modulator core performs the digital baseband functionality for the transmission side of Digital Video Broadcasting S…
The MW_DAB modulator core performs the digital baseband function for the transmission side of new generation Digital Audio Broadc…
DVB-RCS and WiMAX Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible DVB-RCS and IEEE 802.16 WiMAX error control decoder.
The FFT1024 core implements 1024 or 512 point FFT in hardware.