Vendor: Xilinx, Inc. Category: Channel Coding

3GPP Mixed Mode Turbo Decoder

The 3GPP Mixed Mode Turbo Decoder provides a flexible turbo convolutional decode function for both LTE and UMTS air interfaces.

Overview

The 3GPP Mixed Mode Turbo Decoder provides a flexible turbo convolutional decode function for both LTE and UMTS air interfaces.  The implementation is compliant with the requirements set out in 3GPP UMTS and LTE specifications.  The product provides an optimized turbo decode function for basestations at all form factors, from femto to macrocells.

Key features

  • Support for LTE only, UMTS only or both
  • Compliant with 3GPP TS 25.212 and TS 36.212 Release 10
  • Dynamic decoding of LTE and UMTS data on a block by block basis
  • Configurable with either 1, 2, 4 or 8 decode units, allowing resource optimization based on system needs
  • Integrated scheduler ensures that decode latency remains constant with variable block sizes
  • Support for MAX, MAX_SCALE and MAX algorithms
  • Support for AXI4-Stream  interface
  • Supported by behavioral C model (with Matlab interface) and testbench

Specifications

Identity

Part Number
EF-DI-MM-TCC-DEC-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

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Frequently asked questions about Channel Coding IP cores

What is 3GPP Mixed Mode Turbo Decoder?

3GPP Mixed Mode Turbo Decoder is a Channel Coding IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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