Overview
The Zaltys DVB-S2 Demodulator (DVBS2-D) IP core is a variant of the Zaltys HDRM-D2 demodulator core which implements a DVB-S2 compliant demodulator. The core accepts I & Q complex baseband samples from an external RF front-end through dual-ADCs. The demodulator output is a sequence of symbols, nominally positioned at the specified constellation points, intended to drive an external LDPC / BCH soft-decision FEC decoder to recover the MPEG transport stream data.
In order to deliver excellent performance, the design utilizes multiple gain control stages within the data path to maximize dynamic range. Up to four sets of matched root-raised cosine filter coefficients can be incorporated into a given implementation, allowing four excess bandwidth values for the input signal to be selected in software. All aspects of the timing and carrier recovery are fully programmable, including loop filter coefficients and lock detector thresholds. In addition, monitoring registers provide a high degree of software visibility for parameters such as frequency offsets, lock levels and SNR estimation.
The demodulator datapath consists of six distinct sections. These correspond to the Radio Interface, Decimator, Timing Recovery, Adaptive Equaliser, Framing Acquisition, and Carrier Recovery functions. The overall operation of the system is automatically managed by an integrated Finite State Machine controller. Communications with the core is handled by a 32-bit Simple Microprocessor Interface (SMPI).
Learn more about Modulation Demodulation IP core
This paper focuses on how direct RF sampling architecture has proved to be a felicitous approach for RF data conversion. The progress in converter technology has made it possible to increase the sampling rates and support very large bandwidth and multiple operating RF bands.
Synopsys is now shipping support for Bluetooth® 5.4, the latest specification from the Bluetooth SIG (Special Interest Group). The enhancements in Bluetooth 5.4 will open additional markets and use cases. This is one of the many inflection points in the Bluetooth Low Energy market that will be discussed in this paper.
Carriers are now deploying 5G across the globe driven by the need to keep up with relentless mobile data growth. 5G New Radio (NR) operates at higher frequencies to increase bandwidth, but at the expense of range. There will therefore be a need for a much larger number of 5G RUs to provide the same coverage. The availability of cost-effective, reliable and open 5G radio units is therefore critical.
This paper presents the design and performance of a key RF circuit necessary for the realization of a reconfigurable, integrated RF front-end: a tunable frequency, selectable bandwidth, on-chip, “SAW replacement” filter. The on-die tunable filter presented here has a tunable center frequency up to 1 GHz, a selectable bandwidth up to 40 MHz, and an adjacent channel rejection down to 60 dB.
To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design.
An efficient IP reuse strategy relies on IP blocks with wide applicability. That makes generic blocks, such as programmable processors preferable. However, in many applications such as handheld wireless terminals, additional silicon area and power consumption compared to fixed function solutions can not be accepted.
