High Data Rate Modulator

The Zaltys High Data Rate Modulator (HDRM-M) IP core efficiently realizes the digital baseband section of a high performance modem transmit path, including symbol mapping, matched filtering, sample interpolation, and DAC interfacing. Using sophisticated DSP techniques, the core can generate almost any modulation scheme up to 8 bits wide, such as (but not restricted to) BSPK, QPSK, offset- QPSK, 8/16/32/64/128/256QAM, 16/32APSK, and various “non-square” (NS) schemes, all to a high performance level and at high symbol rates. The modulator is highly flexible, supporting continuously variable software-selectable symbol rates of between 2.5 kbaud and 40Mbaud, when operating with a fixed 100MHz system/DAC clock rate. This is the typical performance achievable when implementing the design using inexpensive FPGA devices, but increased data rates are possible by targeting the design to higher performance FPGA families which allow an increase in system clock rate. Once configured via the 32-bit microprocessor interface, the modulator operation is completely automatic .

• Versatile digital modulation engine
• Programmable constellation mapper supports multiple constellations from BPSK to 256QAM
• Supports offset-QPSK (OQPSK)
• Supports continuously variable symbol rates
  • Internal filter interpolates up to a factor of 8192
  • Supports typical rates of 2.5 kbaud to 40Mbaud with 100MHz clock (range scales linearly with clock frequency)
• Integrated transmit symbol rate NCO
• FLL (frequency-locked-loop) allows transmit symbol rate to be locked to an external reference
• Matched filter with fully programmable alpha from 20% upwards
• Programmable 2’s complement or offset-binary 8, 10, 12 or 14- bit DAC I & Q interfaces
• Versatile FIFO input accepts n-bit symbols (1 ≤ n ≤ 8) or raw I / Q constellation point coordinates
• Built- in sin( x) / x DAC compensation filters and internal gain and offset calibration
• Highly configurable and versatile - fully programmable via simple microprocessor interface (SMPI)
• Suitable for FPGA or ASIC implementation
• Xilinx Virtex® - 6 implementations support over 100Mbaud (800Mb/s throughput) with 256QAM
• Synchronous design with single clock
• Hardware evaluation board (available extra)