IMS: Intelligent Hardware Monitoring System for Secure SoCs
By Wadid Foudhaili 1, Aykut Rencber 2, Anouar Nechi 1, Rainer Buchty 1, Mladen Berekovic 1, Andres Gomez 2, and Saleh Mulhem 1
1 Institute of Computer Engineering, Universität zu Lübeck, Lübeck, Germany
2 Institute of Computer and Network Engineering, TU Braunschweig, Braunschweig, Germany

Abstract
In the modern Systems-on-Chip (SoC), the Ad vanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent counter- measures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations. IMS is a hardware module leveraging neural networks to achieve high detection accuracy. For model training, we perform DoS attacks through header-field manipulation and systematic malicious operations, while recording AXI transactions to build a training dataset. We then deploy a quantization optimized neural network, achieving 98.7% detection accuracy with <=3% latency overhead, and throughput of >2.5 million inferences/s. We subsequently integrate this IMS into a RISC-V SoC as a memory-mapped IP core to monitor its AXI bus. For demonstration and initial assessment for later ASIC integration, we implemented this IMS on an AMD Zynq UltraScale+ MPSoC ZCU104 board, showing an overall small hardware footprint (9.04% look-up-tables (LUTs), 0.23% DSP slices, and 0.70% flip-flops) and negligible impact on the overall design’s achievable frequency. This demonstrates the feasibility of lightweight, security monitoring for resource-constrained edge environments.
Index Terms — AXI protocol security, hardware security monitoring, ML-based monitoring, SoC security, protocol-level at tacks, denial-of-service, RISC-V.
To read the full article, click here
Related Semiconductor IP
- Verification IP for AMBA AXI
- Multi-Channel AXI DMA Engine
- AXI Bridge for PCIe IP Core
- AXI Bridge with DMA for PCIe IP Core
- Siemens EDA* AXI Verification IP Suite
Related Articles
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
- Only secure hardware can safeguard standards
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST