High-reliability decoding that repairs corrupted bits on noisy links and performs close to the theoretical limit.
- LDPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
High-reliability decoding that repairs corrupted bits on noisy links and performs close to the theoretical limit.
No connectivity required. No companion DSP.
CCSDS SCCC Demapper and Turbo Decoder
4 state CCSDS compatible serially concatenated convolutional code (SCCC) demapper and turbo decoder
Fully compliant with UCIe v3.0 specification (August 2025); backward compatible with UCIe v2.0, v1.1, and v1.0
SmartDV’s UCIe 2.x Controller IP is a silicon-proven, fully featured Universal Chiplet Interconnect Express solution purpose-built for SoC and multi-die system designs r…
OpenTitan-based RISC-V Secure Element
Customized System-on-Chip Solutions for Sovereign and Future-Proof Security
Time-Sensitive Networking (TSN) End Point DO-254 IP Core
Compliant with IEEE 802.1DP-2025 Synchronous Type 2 End Station requirements
Graphics, compute and AI all on one processor, with one software stack
Mesochronous Bridge for PCIe/CXL
Timing-Agnostic PCIe/CXL Bridge for Prototyping & Emulation
Desktop-class graphics within a mobile power budget
Fully compliant with OpenGMSL v3.0
Fully compliant with OpenGMSL v3.0 specification (March 2026)
Switched Capacitor 3.6V Boost-Buck DC-DC Converter
DC-DC Switched Capacitor Boost-Buck Converter IP in X-FAB XC018-0.18µm CMOS
Cloud and Data Center Compute Subsystem
Fast, scalable, and flexible Arm Neoverse CSS N4 is the most configurable Neoverse compute subsystem, with flexible options for CPU cores, cache sizing, memory, and I/O.
Protocol-Neutral Custom Fabric
Flexible, software-defined fabric IP for custom protocols, AI workloads, and chiplet-scale systems.
Configurable Cache Coherent Fabric IP
Scalable Coherent Connectivity for Advanced SoCs and Chiplet Systems
Configurable AMBA Non-Coherent Fabric IP
Flexible, High-Performance Connectivity for SoCs and Chiplet Systems Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficientl…
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
Compliant to NIST FIPS PUB 197
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP