CAN 2.0 B Compatible Network Controller
The logiCAN core provides all features expected from the standard CAN network controller.
- CAN / CAN-FD / CAN-XL
- now
- In compliance with CAN 2.0A…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
CAN 2.0 B Compatible Network Controller
The logiCAN core provides all features expected from the standard CAN network controller.
The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
softDSP released 3GPP compliant Turbo decoder IP core in May, 2000.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
This is a high speed 8 state 3GPP™ (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible paralle…
Very High Speed 8 State MAP Decoder
This is a very high speed 8 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wit…
Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
100-10Gbps Ethernet MAC Controller
LeWiz provides a range of Ethernet MAC controllers from 100Gbps to 10Mbps for use in space, defense, and ultra-low latency applications.
Deep-learning noise reduction IP core
Deep-learning spatial noise reduction + temporal noise reduction
Bring programmable neural processing closer to infrastructure data
C2C (Chip-to-Chip) interface IP
C2C & D2D Combo (UCIe-based) IP compliant with UCIe specification
Supports ONFI 5.1/5.2/6.0 Specification and NV-DDR3/NV-LPDDR4 up to 3600/4800/5600/6400 Mbps
Compatible with JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
Verification IP for MIPI SoundWire
Achieves rapid verification closure of MIPI SoundWire devices operating with Basic and High-PHY links
A image pipeline that turns raw sensor data into a clean, colour-correct image in real time.
All-hardware H.265/HEVC processing, including H.264 to H.265 transcoding for real-time 4K video.
An all-hardware H.264/AVC pipeline for real-time, low-latency video on FPGAs, suited to UAV and ISR links.
Peak cancellation that lowers the peak-to-average power ratio before the PA, so it can run more efficiently.
Adaptive linearization of RF power amplifiers, so the amplifier can run closer to saturation with less distortion and higher efficiency.
A multicarrier transmit and receive baseband that keeps wireless links working through multipath and fading.