Power On Reset on TSMC CLN28HPC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
- TSMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Power On Reset on TSMC CLN28HPC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN16FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on TSMC CLN12FFC
The Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrate…
Power On Reset on GLOBALFOUNDRIES 12LP+
The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
Power On Reset on GLOBALFOUNDRIES 12LP
The Power-On Reset (POR) and Over Current Detection (OCD) macro comprehensively addresses typical SOC start-up power supply monit…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3P-CLN3X
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3E
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).