CCSDS SCCC Demapper and Turbo Decoder

The SCD02C is a fully compatible CCSDS SCCC [1] error control decoder. Nineteen different interleaver sizes from 8640 to 65520 bits are implemented. Twenty seven different code rates R from 0.355 to 0.899 can be selected, giving bandwidth efficiencies from 0.711 to 5.392 bit/sym, excluding header and pilot symbols.

For the code, both the outer and inner encoders use a four state rate 1/2 systematic recursive convolutional code. The outer rate 1/2 code is punctured to a rate of 2/3. The outer four bit tail is punctured to three bits. The inner rate 1/2 code uses different forms of puncturing for the systematic and parity bits, with the four bit tail not punctured. The interleaver size is of size I = 1.5K+3, where K is the number of information bits, which ranges from 5758 to 43678.

The number of coded bits is 8100s, where s is the number of bits per symbol, ranging from s = 2 for QPSK to 6 for 64APSK. To allow continuous decoding, a ping–pong symbol deinterleaver is used to buffer the input data to be decoded. For the turbo decoder, a ping–pong output memory is used to output the decoded data.

Np = 60 MAP02C four state rate 1/2 MAP decoder cores are used with the SCD02CF core, to iteratively decode the SCCC turbo code. The suffix F for the core name indicates the use of 60 MAP decoders. Suffixes 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and G correspond to Np = 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 20, 24, 30, 40 or 120, respectively.

The Log–MAP algorithm for maximum performance or the max–log–MAP algorithm for minimum complexity and highest speed can be selected. The extrinsic information can be optionally scaled and limited with each half iteration, improving performance with max–log–MAP decoding.

The reverse sliding window algorithm is used with sliding window lengths of L = 32 or 64 for Kd/Np > L and L = Kd/Np otherwise, where Kd = I for inner decoding and Kd = K+2 = 2I/3 for outer decoding. Eight–bit quantisation is used for near optimum performance.

The turbo decoder can achieve up to 787 Mbit/s with 10 iterations and max–log–MAP decoding using a 356 MHz internal clock (ACM = 27, Np = 60). Log–MAP decoding decreases speed by about 24%. Optional early stopping allows the decoder to greatly reduce power consumption with little degradation in performance.

The VHDL cores can be used with Xilinx Integrated Software Environment (ISE) or Vivado software to implement the core in Xilinx FPGA’s. VHDL cores are available on request for ASIC, Intel/Altera, Lattice and Microsemi/ Actel designs.

Table 1 shows the resources used for Kintex UltraScale+ devices. Resources for Virtex–5, Virtex–6, Spartan–6, 7–Series and UltraScale devices are similar to those for UltraScale+. The MODE input can be used to select various decoder implementations. Three clocks are used for the input symbols, turbo decoder and decoded data. No other resources are used.

Table 1: Resources used.

Table 2 shows the PCD02CF performance achieved with various Xilinx parts and K = 43678 (ACM = 27). Tcp is the minimum clock period over recommended operating conditions. These performance figures may change due to device utilisation and configuration. Note that Zynq devices up to XC7Z020 and from XC7Z030 use programmable logic equivalent to Artix–7 and Kintex–7 devices, respectively.

Table 2: Performance of Xilinx parts.

MODE = 0, Id = 10, ACM = 27, L = 32, Np = 60

Signal Descriptions

The MODE input is used to select various decoder implementations. Note that MODE is a “soft” input and should not be connected to input pins or logic. This input is designed to minimise decoder complexity for the configuration selected.

• 4 state CCSDS compatible serially concatenated convolutional code (SCCC) demapper and turbo decoder
• Code rates from 0.355 to 0.899
• Data lengths from 5758 to 43678 bits
• Interleaver sizes from 8640 to 65520 bits
• Optional QPSK, 8PSK, 16APSK, 32APSK and 64APSK demapping and deinterleaving with 10–bit inphase and quadrature two’s complement input
• Optional demapped 8–bit sign magnitude log– likelihood–ratio (LLR) input
• Includes ping–pong input and output memories
• Optional log–MAP or max–log–MAP constituent decoder algorithms
• 60 parallel MAP decoders (1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 20, 24, 30, 40 or 120 parallel MAP decoders on request)
• Up to 356 MHz internal clock
• Up to 787 Mbit/s (146 Msym/s) with 10 decoder iterations
• Up to 64 iterations
• Programmable signal points option
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• Estimated channel error output
• Free simulation software
• Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.