Vendor: Arm Ltd. Category: CPU

Cloud and Data Center Compute Subsystem

Fast, scalable, and flexible Arm Neoverse CSS N4 is the most configurable Neoverse compute subsystem, with flexible options for CPU cores, cache sizing, memory, and I/O.

Overview

Fast, scalable, and flexible

Arm Neoverse CSS N4 is the most configurable Neoverse compute subsystem, with flexible options for CPU cores, cache sizing, memory, and I/O. Silicon designers can target single or multi chiplet systems with Arm's most performant Neoverse N core to date and take advantage of additional time-to-market optimizations over previous CSS generations.

 

Built for next-generation agentic AI data centers, Neoverse CSS N4 delivers rack-scale CPU density, efficient control-plane processing for high-bandwidth network, and high-speed interfacing with AI accelerators. It provides the compute foundation for DPUs that offload security and networking, accelerate AI KV-caching, and isolate agentic AI workloads from the host. Backed by nearly a decade of Neoverse deployments and close partner collaborations, Arm Neoverse CSS N4 provides the fastest path to custom silicon for the agentic AI data center.

Inside Neoverse CSS N4

The building blocks of the Neoverse CSS N4 platform

  • Configurable from 8 to 128 CPU cores per die
  • The first N-Series CSS supporting CPU frequencies up to 3.8 GHz
  • The first Neoverse CSS to support LPDDR6 memory and PCIe Gen 7

Specifications

Feature 3nm Specification
Number of CPU cores
  • Up to 128 cores
  • Up to 3.8GHz
Cache Hierarchy
  • L1: 64KB I-cache, 64KB D-cache (private, parity)
  • Configurable up to 2MB L2 private cache with ECC
  • Configurable up to 256MB shared system-level cache (SLC) with ECC 
Memory I/O
  • Provides standard AMBA CHI, AXI interfaces to support
  • Up to 128 lanes PCIe Gen7/6
  • CXL 4.0
  • Bifurcation support up to x4 for each x16 PCIe lanes 
Die-to-Die Connectivity
  • Supports multi-chiplet/multi-socket die-to-die connectivity using AMBA CHI C2C protocol
  • UCIe or partner-specific PHY supported
General I/O Expansion interface to connect slower speed peripheral. For example, USB, I3C, QSPI
System Management AST2600 BMC over PCIe, SCP, MCP (on-chiplet system management controller)

Key features

Most configurable Neoverse CSS:

  • Configure the number of CPU cores, cache sizing, memory, I/O, accelerator connectivity and chiplet interfaces.

Built for agentic AI:

  • Power agentic AI infrastructure with up to 2x performance per socket, 1.25x performance per watt and 1.75x memory bandwidth versus the previous generation.

Accelerate the path to production silicon:

  • Start development earlier and reduce integration effort with a pre-integrated subsystem and early access to development resources.

Block Diagram

Specifications

Identity

Part Number
Arm Neoverse CSS N4
Vendor
Arm Ltd.
Type
Silicon IP
Application
Data center , Edge AI

Compute

CPU Architecture
ARM

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Great Britain

Learn more about Arm Neoverse CSS N4 IP core

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What is Cloud and Data Center Compute Subsystem?

Cloud and Data Center Compute Subsystem is a CPU IP core from Arm Ltd. listed on Semi IP Hub.

How should engineers evaluate this CPU?

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