DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.
This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
DDR-I/II/III CONTROLLER IP CORE
DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targ…
AXI External Memory Controller
The AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…
XPS Multi-Channel External Memory Controller (SRAM/Flash)
The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynch…
Multi-Port Memory Controller (DDR/DDR2/SDRAM)
MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory.
The SRAM-CTRL implements a Static Random Access Memory (SRAM) Controller translating AHB, or AXI4, or APB bus reads and writes in…
DDR2 SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
DDR SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
DDR SDRAM Controller
LPDDR6 PHY & Controller
The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode.
AMBA AHB Bus to DDR SDRAM Controller
AMBA AHB Bus to DDR SDRAM Controller
DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP
DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements…
High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC…
Dolphin Technology's hardened DDR5/4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven.
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 SDRAM Controller IP Core Pinout Utility
Overview The DDR3 Pinout Generation Utility is a GUI tool that is capable of generating the pinout and preference files that cont…
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process