Designing DDR3 SDRAM controllers with today's FPGAs
This article outlines the major differences between DDR3 and DDR2 SDRAM architecture and reviews them in the context of an FPGA-based reference design tested in hardware at 800 Mbps.
Vendor:
Xilinx, Inc.
Category:
DDR
Multi-Port Memory Controller (DDR/DDR2/SDRAM)
MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory.
Overview
MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory. MPMC provides access to memory for one to eight ports, where each port can be chosen from a set of Personality Interface Modules (PIMs) that permit connectivity into PowerPC® 405 processor and MicroBlaze™ processors using CoreConnect® PLBv4.6 and the MPMC Native Port Interface (NPI) structures, and well as a a Memory Interface Block (MIB) PIM (PPC440MC) for the PowerPC 440 Processor.
Key features
- Soft Direct Memory Access (SDMA) support
- Double Data Rate (DDR/DDR2) and Single Data
- Rate (SDR) SDRAM memory support
- DIMM support (registered and unbuffered)
- Error Correcting Code (ECC) support
- Parameterizable number of ports (1 to 8)
Specifications
Identity
Part Number
Multi-Port Memory Controller (DDR/DDR2/SDRAM)
Vendor
Xilinx, Inc.
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR2
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is Multi-Port Memory Controller (DDR/DDR2/SDRAM)?
Multi-Port Memory Controller (DDR/DDR2/SDRAM) is a DDR IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.