How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Novo Space
Category:
DDR
NAND Memory Controller
The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode.
Overview
The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode. This core also supports error correction on the fly without any processor intervention. Up to 8 memory chips can be accessed on the same bus with write speed of 100Mbps and read speeds of 120Mbps. Support for Linux OS is already implemented and it is included with the IP core, alowing to use UBIFS and JFFS. The design is already optimized and tested for all Novo Space's products including Microchip SmartFusion2® and Xilinx Zynq UltraScale+®
This IP core comes in different versions:
- AXI/AXILite: Ready to connect to a AXI/AXILite bus. It has a AXILite slave to be configured and a AXI full interface to read/write data from memory
- AHB/APB:Same concept as AXI/AXILite configuration but with APB slave for configuration and AHB to write memory
SPECIFICATIONS
| NV-DDR I/O | No |
| Multi chip/lun | Up to 8 |
| Onfi version | 2.1 |
| Page/OOB size | Configurable to support any NAND chip |
| ECC Algorithm | Configurable Hamming code depending on chip specs (typically Hamming (72,64)) |
Specifications
Identity
Part Number
NAND Memory Controller
Vendor
Novo Space
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is NAND Memory Controller?
NAND Memory Controller is a DDR IP core from Novo Space listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.