How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Dolphin Technology
Category:
DDR
DDR PHY
Dolphin Technology's hardened DDR5/4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven.
Overview
Dolphin Technology's hardened DDR5/4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven. Combo PHYsupporting speeds upto 4266 Mbps. It is fullycompliant with the DFI 5.0 specification, and features include slew rate control, per-bit de-skew, gate training, read andwrite leveling and built-in self-test (BIST).
It also complies to Automotive standard AEC-Q100 with Fault coverage 99.8%.
Inaddition, our PHY IP is optimized to provide a complete solution when combined with Dolphin's DDRx and LPDDRx SDRAM Memory Controller IP.
| DDR PHY (HARD IP) | 2/3nm | 4/5/6/7nm | 12/16nm | 28nm | 40nm | 55nm | 65nm |
| DDR5/4/3/2 PHY (DFI 5.0 compliant) | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| LPDDR5/4x/4/3/2 PHY (DFI 5.0 compliant) | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| DDR3/2 PHY (DFI 4.0 compliant) | 🟢 | 🟢 | 🟢 | ||||
| Maximum speed, with 1.8V oxide (Mbps) | 6400 | 4266 | 3200 | 3200 | 2133 | 1600 | 1600 |
| Maximum speed, with 2.5V oxide (Mbps) | 1600 | 1600 | 1600 | 1600 | 1600 | 1600 | 1600 |
| IP is split into two hard macros (one for commands, control and address pins, one for 8-bit data bus) | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Supports custom number of address bits | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Compensation controller and pads for automatic driver and receiver termination impedance calibration | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Slew rate control, per-bit de-skew, gate training, read and write leveling | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| JTAG signals for Mentor/Synopsys and LogicVision | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| BIST with Pseudo Random Pattern Generator | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Loopback mode | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Scannable flops | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | ||
| Wirebond, flip-chip and cup configurations | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| DDR CONTROLLER (SOFT IP) | 2/3nm | 4/5/6/7nm | 12/16nm | 28nm | 40nm | 55nm | 65nm |
| DFI 5.0 Interface with Matching, 1:2 or 1:4 Frequency Ratio | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Built-in Gate Training and Read/Write Leveling | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Maximum speed (Mbps) | 6400 | 4266 | 3200 | 2133 | 1600 | 1600 | 1600 |
| JEDEC Standard DDR5/4/3/2 and LPDDR5/4/3/2 SDRAM | 🟢 | 🟢 | 🟢 | 🟢 | |||
| JEDEC Standard DDR3/2 and LPDDR2 SDRAM | 🟢 | 🟢 | 🟢 | ||||
| Multi-port configurable AXI4 interface w/QoS signaling | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Multi-port arbitration engine with programmable dynamic priority algorithm | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Pipeline Arbitration Option for Frequency vs. Latency Tradeoff | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Fully configurable for various performances and requirements | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| FPGA portable (Xilinx PHY & Altera PHY compatible) | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| BFM verification suite | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Single AXI4-Lite, APB programming interface | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| AXI4 dynamic QoS signaling for non-blocking communications | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Support for low-latency bypass ports/channels | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Advanced dynamic QoS support based on Queuing Theory and Traffic Hysteresis | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Sideband and Inline ECC scheme | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Dynamic Address Mapping Scheme | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Multiple Burst Priority Arbitration Scheme | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Internal Intelligent Bank Management and Auto-precharge Scheduling | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Intelligent Traffic Direction Aggregation and Switching | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| Automatic Periodic Refresh, Automatic Periodic ZQ Calibration | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
Specifications
Identity
Part Number
DDR PHY
Vendor
Dolphin Technology
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is DDR PHY?
DDR PHY is a DDR IP core from Dolphin Technology listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.