How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Eureka Technology, Inc.
Category:
DDR
AMBA AHB Bus to DDR SDRAM Controller
AMBA AHB Bus to DDR SDRAM Controller
Key features
- External pin reduction by transferring 2 bits of data per pin.
- Supports multiple external SDRAM banks.
- Automatic refresh generation with programmable refresh intervals.
- Self-refresh mode to reduce system power consumption.
- Standard delay cells or user provided DLL for DQ and DQS alignment.
- Integrated data buffer synchronizes user interface with DDR SDRAM data.
- Operates on both discrete DDR SDRAM chips and DDR SDRAM DIMM.
- Programmable memory size: 4, 8, and 16 bits per SDRAM.
- Programmable SDRAM access timing parameters.
- Automatic refresh generation with programmable refresh intervals.
Block Diagram
EP534 block diagram
Specifications
Identity
Part Number
EP534
Vendor
Eureka Technology, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is AMBA AHB Bus to DDR SDRAM Controller?
AMBA AHB Bus to DDR SDRAM Controller is a DDR IP core from Eureka Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.