Vendor: Atria Logic, Inc. Category: DDR

DDR-I/II/III CONTROLLER IP CORE

DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targ…

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Overview

DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targeted for System-on-Chip (SoC) and FPGA platforms. The memory controller core is fully configurable to accommodate all the features in the JEDEC specification. The design has set of programmable registers to define the functionality of the memory controller and to configure the DRAM. On power-up the controller performs initialization of the DRAM based on the programmed paramerters in the registers. On completion of the initialization sequence, the DRAM will be ready to process READ/WRITE requests from the user. In case of multiple port access, an efficient Arbiter is used with programmable management scheme to have a fair arbitration. The controller also provides logic to support low-power applications by implementing SELF REFRESH and POWER-DOWN modes.

The controller core has the following modules:

Control and Timing Engine
DRAM Initialization Engine
Command Generation Engine
Address Generation and Bank Management
Refresh Generation Engine
Multiport Weighted Round-robin Arbiter
Write Path and Read Capture Logic
Calibration Logic
PHY Logic for DDR I/O


The AL_DDR12_CTRL Core is designed for performance with low latencies and maximum bandwidth allocation for up to 16 requestors. The AL_DDR12_CTRL Core is highly configurable allowing the user with several options such as: DRAM width, DRAM instance count, DRAM speed grade, DRAM CAS latencies, number of user ports for DRAM access. The Controller Core flexible user interfaces such as: Command/Data FIFO or AMBA-AHB or Altera Avalon Slave interfaces for easy SoC integration.

 

Key features

  • Compliant with JEDEC Standard.
  • Support up to 4 Gb and 8 banks of DDR2 devices.
  • Application bus – FIFO, AHB, Avalon. Support multiple agents on application bus interface with built-in credit/aging based weighted round robin arbitration scheme.
  • Programmable CAS latency and DRAM timing parameters.
  • Programmable auto-refresh time interval.
  • Support power down, self refresh.
  • Auto initialization of memories.
  • Configurable address mapping between application and DRAM bank/row/column address.
  • Auto-calibration scheme for DDIO interfaces, support for ondie termination and off chip driver impedance adjustment.
  • Support back to back WR, RD commands with min timing.
  • High data rate of memory throughput
  • Choice of 16/32/64 DDR bus widths

Block Diagram

AL_DDR3_CTRL block diagram

Specifications

Identity

Part Number
AL_DDR3_CTRL
Vendor
Atria Logic, Inc.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

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Provider

Contact Atria Logic, Inc.

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Frequently asked questions about DDR Interface IP

What is DDR-I/II/III CONTROLLER IP CORE?

DDR-I/II/III CONTROLLER IP CORE is a DDR IP core from Atria Logic, Inc. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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