Learn more about DDR IP core
INNOSILICON Technology today officially announced the launch of its comprehensive high-speed UALink (Ultra Accelerator Link) solution portfolio, featuring industry-leading single-lane 112G/224G high-performance PHY technology.
Recently, Innosilicon Technology, a seasoned player with nearly 20 years of expertise in the IP industry, has announced a major milestone: its self-developed LPDDR6/5X ComboPHY+controller IP has been successfully signed and delivered to a leading industry client.
At the event, the company will showcase its leadership in ready-to-deploy AI solutions, featuring high-speed memory, SerDes, and chiplet subsystems, with a spotlight on its LPDDR6/5X Combo offering.
Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.
Pioneering the industry, Innosilicon has deployed two fully-compatible upgrade solutions LPDDR5/5X/4/4X Combo IP and DDR5/4 Combo IP across multiple global mainstream 28nm and 22nm process nodes, effectively helping customers tackle supply chain upgrade challenges.
This white paper will discuss the design challenges that IC designers are facing when developing the new GDDR 7 high-performance memory interface and highlight some of the possible solutions to overcome these challenges, ensuring compliance and robustness of the GDDR7 memory interface.
