Designing DDR3 SDRAM controllers with today's FPGAs
This article outlines the major differences between DDR3 and DDR2 SDRAM architecture and reviews them in the context of an FPGA-based reference design tested in hardware at 800 Mbps.
Vendor:
Xilinx, Inc.
Category:
DDR
XPS Multi-Channel External Memory Controller (SRAM/Flash)
The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynch…
Overview
The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynchronous SRAM and Flash memory devices through the MCH or PLB interfaces. It is assumed that the reader is familiar with the PLB and MCH protocol.
Key features
- Connects as a 32-bit slave on PLB v4.6 bus of 32, 64 or 128 bits
- Can be used with PLB interface only or MCH interface only or in combination of both PLB and MCH interfaces
- Supports multiple (up to 4) external memory banks
- Supports single-beat and burst transactions
Specifications
Identity
Part Number
XPS Multi-Channel External Memory Controller (SRAM/Flash)
Vendor
Xilinx, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is XPS Multi-Channel External Memory Controller (SRAM/Flash)?
XPS Multi-Channel External Memory Controller (SRAM/Flash) is a DDR IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.