DDR Interface IP Cores

The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules.

• Controller

The QDR II SRAM Controller Intel® FPGA IP function provides an easy-to-use interface to QDR II SRAM modules.

• Controller

The Intel FPGA Intellectual Property (IP) for DDR3 SDRAM High-Performance Controller provides simplified interfaces to industry-s…

• Controller
• DDR3

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

• Controller + PHY
• DDR2

The High-Performance Memory Controller II SDRAM Intel FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM…

• Controller

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managi…

• Controller
• DDR2

DDR5 Verification IP supports data rates up to 8400 MT/s, ensuring high-performance memory controllers meet the latest standards …

• Controller
• DDR5

LPDDR5 Verification IP (VIP) is a tool designed to simulate and validate the functionality of LPDDR5 memory controllers.

• Controller

The GDDR4 Controller Verification IP (VIP) ensures robust simulation and validation of GDDR4 memory controllers in SoC designs.

• Controller
• DDR4

The DDR4 Memory Controller Verification IP ensures compliance with DDR4 standards, validating high-speed data transfer, read/writ…

• Controller
• DDR4

solution for extensive and fast verification used by multiple production designs.The Cadence® Verification IP (VIP) for DFI provi…

• Verification IP
• Controller

First to market with full DDR5 DIMM support.This Cadence Verification IP (VIP) provides support for the JEDEC DDR5 SDRAM Unbuffer…

• Verification IP
• Controller
• DDR5

In production since 2014 on dozens of production designs.This Cadence® Verification IP (VIP) supports the JEDEC® Memory Device DD…

• Verification IP
• Controller
• DDR5

First to market with full DDR4 LRDIMM support.This Cadence® Verification IP (VIP) supports the JEDEC® DDR4 Unbuffered DIMM (UDIMM…

• Verification IP
• Controller
• DDR4

In production since 2011 on dozens of production designs.This Cadence® Verification IP (VIP) supports the JEDEC® Low Power Memory…

• Verification IP
• Controller
• DDR4

The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…

• Controller + PHY + 1

The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…

• Controller + PHY + 1

The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…

• Controller + PHY + 1
• DDR4

The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…

• Controller + PHY + 1
• DDR4

The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…

• Controller + PHY + 1
• DDR4