Learn more about DDR IP core
This is a two-part article that focuses on the design guidelines and describes how to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions.
This article examines the architecture behind the I/O blocks in high-end FPGAs and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.
To achieve a robust high data rate, such as 667 Mbps in a DDR2 system, a dynamic auto-calibration PHY IP core significantly simplifies the memory interface design
Wirebond package,lower cost package with lesser IO density always impose challenge for FPGA designer to meet the required power parameteric budget.This paper will share 5 watch outs on wirebond chip power bus planning.
Brett Murdock, Dana Neustadter (Synopsys)