Vendor:
Altera
Category:
DDR
RLDRAM II Controller Intel® FPGA IP
Overview
Key features
- Support for industry-standard RLDRAM II components
- Common I/O (CIO) and separate I/O (SIO) device support
- Flexible and robust design
- Non-multiplexed addressing
- Datapath generation
- Data strobe signal (DQS) and non-DQS capture modes
- Intellectual property (IP) functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators
- Easy-to-use IP Toolbench interface and automatic constraint generation
- This IP is included in the IP Base Suite which is bundled with Intel® Quartus® Prime Standard and Pro Edition Software.
Specifications
Identity
Part Number
RLDRAM II Controller Intel® FPGA IP
Vendor
Altera
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about DDR Interface IP
What is RLDRAM II Controller Intel® FPGA IP?
RLDRAM II Controller Intel® FPGA IP is a DDR IP core from Altera listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.