Simulation VIP for DDR5 DIMM

First to market with full DDR5 DIMM support.

This Cadence Verification IP (VIP) provides support for the JEDEC DDR5 SDRAM Unbuffered, Registered, and Load-Reduced DIMM Design Specification, the DDR5 UDIMM/RDIMM/LRDIMM standard. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 DIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 DIMM is the next-generation DIMM specification with improvements in the areas of speed, configurability, reliability, and power saving. It supports speeds up to 4800 speed grade. With redefined Control Word Write, DRAM Mode register write interface, and control word settings like programmable latencies and encoded quad modes, it is more flexible. Guarding of the command forwarded to DRAMs and the RCD Control word writes with optional parity checking and detailed specification for different ways of recovery in the case of parity errors makes this more reliable.

Supported specifications: JEDEC DDR5 SDRAM Rev 1.01, JEDEC DDR5RCD01, and JEDEC DDR5DB01.

• DIMM Types
• DDR5 UDIMM, RDIMM, and LRDIMM
• Size
• 32Gb, 64Gb, and 128Gb
• Speed
• 3200, 3600, 4000, 4400, and 4800
• DRAMs
• x4 and x8
• DIMM Configuration Support
• Supports up to 2 ranks and dual independent channels
• Configurable DIMM Topology
• Number of ranks and components with and the overall interconnect between DIMM, RCD, and DRAM are configurable using SOMAs
• DRAM Features
• Supports all DDR5 SDRAM features as stated in DDR5 MM product page
• Training
• QCSTM Training
• Core RCD Forwarding Logic
• All DRAM commands
• ECC Checks Bits
• Optional DRAM instantiation for checks bits
• RCD Data Rate
• Supports DDR, SDR1, and SDR2 modes
• Parity
• Optional support for checking even parity, in case of errors: Gate DRAM commands
• Control Word
• Output Delay Control Word for CS, RW04 Control Word
• Weak Driver Support
• Signal strength modeling, users can use pull up or pull down on the input pins and the model will be able to detect the signal strength and function like a real device
• RCD I2C Interface
• RCD for both Byte and Block Mode Write and Read Operations
• RCD Output Delay Modeling
• Supports Output Delay Modeling
• RCD Bus Inversion
• Supports RCD Bus Inversion
• Inter Rank Odt
• Supports Inter Rank Odt Checks
• RDC Self Refresh
• Supports Self Refresh with and without Clock Stop
• DB Independent Nibble Delays
• Supports all the Lower and Upper Nibble Delay settings for each of the two supported ranks
• RCD and DB Control Words
• Directed and Paged Control Words
• Rank Training Control Words
• Periodic Update and Snoop Setting Control Words
• Supports Read/Write (Command/Backdoor) of 100s of Control Words
• DB Power Saving Modes
• Power Down with/without ODT, Self Refresh with/without Clock Stop
• DB BCOM Training
• Supports all the BCOM Training Modes
• DB 1N/2N Command Modes
• Supports both 1N/2N Command Modes
• DB Initialization
• Power-on initialization, Reset with stable power with and without clock stop, ZQ Calibration
• DB Command
• Supports all of BCOM commands
• DB Training Modes
• Transparent Mode and DQ Pass-Through Mode
• DB Addressability Mode
• Support PBA (Per Buffer Addressability) Mode similar to PDA in DRAM
• DB Strobe/Data Training
• Supports all these DB trainings modes: MRE, MRD, DWL, HWL, HIR, HPA