QDR II SRAM Controller Intel® FPGA IP
The QDR II SRAM Controller Intel® FPGA IP function provides an easy-to-use interface to QDR II SRAM modules.
Overview
The QDR II SRAM Controller Intel® FPGA IP function provides an easy-to-use interface to QDR II SRAM modules. The QDR II SRAM Controller ensures that the placement and timing are in line with QDRII specifications.
Key features
- Support for QDR II and QDR II+ SRAMs
- Support for burst of two and four memory type
- Support for 8 bit, 18 bit, and 36 bit QDRII SRAM interfaces
- Flexible and robust design
- Support for two-times and four-times data width on the local side (four-times for burst of four only)
- Automatic concatenation of consecutive reads and writes (narrow local bus width mode only)
- Intellectual property (IP) functional simulation models for use in VHDL and Verilog HDL simulators supported by Intel
- Easy-to-use IP Toolbench interface and example design
- Support for Intel® FPGA IP Evaluation Mode
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about DDR Interface IP
What is QDR II SRAM Controller Intel® FPGA IP?
QDR II SRAM Controller Intel® FPGA IP is a DDR IP core from Altera listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.