DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.
This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.
DDR Controller supporting DDR5 and DDR4 with a CHI interface
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
DDR Controller supporting DDR5 and DDR4
The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standar…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…
Fully compliant with the DFI 4.0
SDRAM Controller DO-254 IP Core
The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as…
The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with …
Fast Cycle RAM (FCRAM) is a DRAM technology with a specialized memory core technology that achieves faster random access times an…
The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory contr…
The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…
DDR/DDR2 SDRAM Controller MACO Core
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.
DDR SDRAM Controller - Non-Pipelined
This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…
The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density.
The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cos…
The Xilinx DDR3 controller is high performance (2133Mbps in UItraScale) with support for lower power DDR3L as well as UDIMMs, SOD…
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process