Vendor: Altera Category: DDR

DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

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Controller + PHY DDR2 View all specifications

Overview

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA IP core work in conjunction with the ALTMEMPHY physical interface IP function. The controllers offer a half-rate interface and a full-rate interface to the customer application logic.

The parameter editor generates a design example, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional delay-locked loop (DLL) (for Intel® Stratix® FPGA series only). The design example is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read-and-write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

Features

  • Flexible architecture
  • Supports industry-standard DDR/DDR2 SDRAM devices and modules
  • Creates a complete DDR/DDR2 solution by bolting onto the ALTMEMPHY Intel FPGA IP physical interface
  • Feature rich
  • Provides full-rate application logic interface
  • Has integrated error correction code (ECC) functionality
  • Offers optional user-controller refresh
  • Supports auto-precharge
  • Supports self-refresh and power-down modes
  • Ease of use
  • Supports Platform Designer (formerly Qsys) IP
  • Offers optional Avalon Memory-Mapped local interface
  • Includes a parameter editor
  • Provides support for Intel FPGA IP Evaluation Mode

Key features

  • Flexible architecture
    • Supports industry-standard DDR/DDR2 SDRAM devices and modules
    • Creates a complete DDR/DDR2 solution by bolting onto the ALTMEMPHY Intel FPGA IP physical interface
  • Feature rich
    • Provides full-rate application logic interface
    • Has integrated error correction code (ECC) functionality
    • Offers optional user-controller refresh
    • Supports auto-precharge
    • Supports self-refresh and power-down modes
  • Ease of use
    • Supports Platform Designer (formerly Qsys) IP
    • Offers optional Avalon Memory-Mapped local interface
    • Includes a parameter editor
    • Provides support for Intel FPGA IP Evaluation Mode

Block Diagram

DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP block diagram

Specifications

Identity

Part Number
DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP
Vendor
Altera
Type
Silicon IP
Controller / PHY
Controller + PHY

Standards & Interfaces

Memory
DDR2

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about DDR IP core

Building high-speed FPGA memory interfaces

This article examines the architecture behind the I/O blocks in high-end FPGAs and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.

5 Wirebond Power Bus Watch Out!

Wirebond package,lower cost package with lesser IO density always impose challenge for FPGA designer to meet the required power parameteric budget.This paper will share 5 watch outs on wirebond chip power bus planning.

Frequently asked questions about DDR Interface IP

What is DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP?

DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP is a DDR IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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