Vendor: Altera Category: DDR

QDR II SRAM Controller Intel® FPGA IP Function

The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules.

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Overview

The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules. The QDR II SRAM controller ensures that the placement and timing are in line with QDR II specifications. The QDR II SRAM controller’s local interface is compatible with the Intel FPGA Avalon® Memory-Mapped interface, for easy integration into Intel Qsys IP.

The QDR II SRAM Controller Intel FPGA IP is optimized for Stratix® series and Cyclone® IV FPGAs. The advanced features available in these devices allow you to interface directly to QDR II SRAM devices.

The IP Toolbench-generated example design instantiates a phase-locked loop (PLL), an optional delay-locked loop (for Stratix II FPGAs only), an example driver, and your QDR II SRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read-and-write commands to the controller and checks the read data to produce the pass/fail and test complete signals. You can replace the QDR II SRAM Controller encrypted control logic in the example design with your own custom logic, which allows you to use the Intel FPGA clear-text resynchronization and pipeline logic and datapath with your own control logic.

This IP is included in the IP Base Suite which is bundled with Intel® Quartus® Prime Standard and Pro Edition Software.

Key features

  • Support for QDR II and QDR II+ SRAMs
    • Support for burst of two and four memory type
    • Support for 8 bit, 18 bit, and 36 bit QDR II SRAM interfaces
  • Flexible and robust design
    • Support for two-times and four-times data width on the local side (four-times for burst of four only)
    • Automatic concatenation of consecutive reads and writes (narrow local bus width mode only)
    • Intellectual property (IP) functional simulation models for use in VHDL and Verilog HDL simulators supported by Intel
    • Easy-to-use IP Toolbench interface and example design
    • Support for Intel FPGA IP evaluation mode

Specifications

Identity

Part Number
QDR II SRAM Controller Intel® FPGA IP Function
Vendor
Altera
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
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Frequently asked questions about DDR Interface IP

What is QDR II SRAM Controller Intel® FPGA IP Function?

QDR II SRAM Controller Intel® FPGA IP Function is a DDR IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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