The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specificati…
The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic. The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices. In some applications, the active controllers can handoff the controller role to the secondary controller on the bus. The Dual role IP joins the I3C bus as a secondary controller (as a target) and will request/accept the controller role. The IP core provides a 32bit AHB bus as application interface to configure and control the transfers. The controller manages the control signal to IO buffers during the active and standby mode. Please note that the User needs to provide appropriate IO buffers to meet the I3C specification.
The I3C Dual Controller implements support for legacy I2C Slave devices, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support. The I3C Dual Controller supports the required SDR mode with Clock frequency of up to 12.5 MHz and also the HDR mode (HDR-DDR) as defined by the I3C Specification.
The following features and capabilities are supported by secondary controller logic
Note: some files may require an NDA depending on provider policy.
I3C Dual/Secondary Controller IP is a I2C / I3C IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
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