The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
Architecture
The SPI bus parameters are highly configurable via registers, the core has configurable ord length, bit ordering and clock gap insertion. All SPI modes are supported and also a 3-wire mode where the core uses one bidirectional data line. In slave mode the core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks. The core can also be configured to automatically perform periodic transfers of a specified length.
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SPI Controller is a SPI / QSPI XSPI IP core from Frontgrade Gaisler listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
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