The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices. The I3C Host Controller IP Core provides a 32-bit AHB bus as the application interface to configure and control the I3C Host Controller IP Core. The I3C Host Controller IP can be easily integrated into an SOC to provide the required I3C functionality. Also, the I3C Host Controller IP provides direct signaling to connect to the IO Buffers (SCL and SDA).
The I3C Host Controller implements support for legacy I2C Device Controllers, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support. The I3C Host Controller supports the required SDR mode with Clock frequency of up to 12.5 MHz and also the HDR modes as defined by the I3C Specification. The included FIFO (Configurable) is used to handle data transfers between IP and the external Device Controllers.
Note: some files may require an NDA depending on provider policy.
I3C Host Controller IP v1.2 is a I2C / I3C IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.