Vendor: Altera Category: Ethernet

10GBASE-R PHY Intel® FPGA IP

The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or…

Contact Provider Request Datasheet

Overview

The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces.

The PHY IP core can be used with either Intel® FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.This PHY IP core is made available as part of the transceiver functionality of the Intel® FPGAs.

Key features

  • PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions.
  • Direct interface with 10GbE MAC for a complete single-chip solution.
  • PHY integrated into hard silicon in Intel® Arria® 10, Stratix® V, and Arria® V GZ FPGAs with 10.3125 Gbps serial transceivers. Soft 10GBASE-R PCS is also available in Stratix® IV GT and Arria® V (GT and ST) FPGAs.
  • Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications.
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation.
  • Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line.
  • Receiver-link fault status detection.
  • Local serial loop-back from transmitter to receiver at serial transceiver for testing.
  • IEEE 1588 v2 option for high precision and accuracy time stamping.
  • High-performance internal system interfaces
    • Intel® FPGA Avalon® Streaming (Avalon-ST) single data rate (SDR) XGMII, 72 bits at 156.25 Mbps for data transfer
    • Intel® FPGA Avalon® Memory-Mapped (Avalon-MM) 32 bits for slave management
  • IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51.
  • Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests.

Block Diagram

10GBASE-R PHY Intel® FPGA IP block diagram

What’s Included?

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Specifications

Identity

Part Number
10GBASE-R PHY Intel® FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about Ethernet IP core

Scalable architectures for high-bandwidth Ethernet line cards

As more consumers receive streaming video in various formats over the Internet, demand for bandwidth continues to increase. However, consumers watching streaming movies via their Xbox or Wii, or viewing YouTube on their computers, are not paying more for the additional gigabits they download each month watching these video feeds. This is one of many factors fueling the demand for higher bandwidth while yielding lower price per gigabit of bandwidth.

Frequently asked questions about Ethernet IP cores

What is 10GBASE-R PHY Intel® FPGA IP?

10GBASE-R PHY Intel® FPGA IP is a Ethernet IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP