ARINC 818 is a point-to-point serial protocol primarily used in avionics applications and supports the transmission of video, aud…
- Video Transport
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
ARINC 818 is a point-to-point serial protocol primarily used in avionics applications and supports the transmission of video, aud…
Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit micropr…
Enhanced Serial Peripheral Interface – Target IP with single, dual, and quad eSPI Bus support for Intel CPU’s
V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment.
V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections.
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specificati…
ARINC 818 Direct Memory Access (DMA) IP Core
ARINC 818 is a point-to-point serial protocol primarily used in avionics applications and supports the transmission of video, aud…
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 12SF+/SF++
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4…
USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication …
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 14SF+
The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwid…
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in UMC 55SP/EF
The combination PHY consists of a Serial ATA (SATA) conforming with the SATA 3.0 Specification, a Peripheral Component Interconne…
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 28SF
The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Spe…
USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption.
JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 55SP
With the JESD204B Tx-Rx PHY IP interface, which fully supports the JESD204B synchronous serial interface, the JESD204B version sp…
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 12SF++
In order to provide full support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is compliant …
MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Displ…
MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification.
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 28SF
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4…
HFT: Packet Filter for NSE's Tick to Trade Protocol for FPGA
In High Frequency trading, Any time spent in examining unwanted packets results in loss of Trading Advantage.
D8530 bridge to APB, AHB, and AXI bus, it is a dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) devic…