USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP
The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interfa…
- Multi-Protocol PHY
- In Production
- Immediate
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP
The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interfa…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.
10M/100M/1G/10G Managed/Unmanaged (TSN) Ethernet Switch IP Core
Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities
MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus.
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SAM 8LPP
The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interfa…
PPA optimized for short reach connectivity
800 Gigabit Ethernet MAC + PCS
The 800Gbps Ethernet IP solution offers a fully integrated Ethernet Technology Consortium (ETC) compliant solution for use in cor…
TTEEnd System A664 Core IP is a RTCA DO-254 DAL A certifiable solution which can be used in integrated modular avionics systems.
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support…
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP
An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX …
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
This PHY IP supports both USB 3.1 Gen1 & Gen2.
World-class, industry-leading, highly scalable, silicon- and PHY-agnostic IP core with 116 Gbps line rate, interoperability tested with leading Serdes providers
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…