Vendor: T2M GmbH Category: Multi-Protocol PHY

12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++

The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specificati…

Overview

The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB High-speed and Full speed), and Serial ATA (SATA) consistent with SATA 3.0 Specification. Because inbuilt power gating control, reference clock control, and more PLL control are supported, lower power consumption is made possible. Additionally, the PHY is broadly usable for diverse circumstances under varying considerations of power consumption because the aforementioned low
power mode option is customizable.

Key features

  • A universal SERDES IP that operation from 1Gbps to 12.5 Gbps
  • Compatible with PCIe/USB3/SATA base Specification
  • Support 40-bit/32-bit/20-bit/16-bit parallel interface
  • Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps)
  • Backward compatible with 2.5Gbps for PCIe
  • Backward compatible with 1.5Gbps, 3.0Gbps for SATA
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis
  • Support TX detect RX function in PCIe and USB3.0 Mode
  • Support Beacon signal generation and detection in PCIe Mode
  • Support LFPS signal generation and detection in USB Mode
  • Support Low Frequency Periodic Signalling (LFPS) generation and detection in USB3.0 Mode
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in SMIC 12nm SF++

Applications

  • PC
  • Television
  • Data storage
  • Multimedia Devices
  • Recorders
  • Mobile devices

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Specifications

Identity

Part Number
12.5G Multiprotocol Serdes IP in 12SFPP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Multi-Protocol PHY IP core

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It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++?

12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++ is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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