eSPI Target IP

DESPI eSPI IP Core – Configurable High-Speed eSPI Target IP for FPGA and ASIC Designs

The DESPI IP Core is a fully configurable Enhanced Serial Peripheral Interface (eSPI) Target IP, compliant with the eSPI Base Specification Revision 1.6. It is designed for high-performance embedded systems, enabling reliable and efficient communication between microcontrollers, embedded controllers (EC), and eSPI-enabled peripherals in Intel-based platforms.

As a modern replacement for the legacy LPC bus, the DESPI IP Core delivers high-speed serial communication with support for single, dual, and quad SPI modes. It operates at serial clock frequencies up to 66 MHz, ensuring low-latency data transfer and optimized system throughput.

Its scalable and flexible architecture allows seamless integration into FPGA and ASIC designs, supporting both single and multi-Target configurations across a wide range of System-on-Chip (SoC) applications.

• eSPI Target IP compliant with eSPI Base Specification Rev. 1.6
• Configurable Target mode (single or multiple Target devices) for complex system architectures (looking for an eSPI Controller? here it is)
• High-speed SPI interface up to 66 MHz for low-latency communication
• Support for Single, Dual, and Quad SPI transfers to maximize bandwidth
• Large, highly configurable shared memory buffer enables efficient and flexible frame and data storage to fit any needs.
• Customizable peripheral channels, including memory-mapped I/O, Virtual Wire signals, and event handling
• Technology-agnostic RTL design compatible with all major FPGA and ASIC vendors
• Optimized for integration into Intel-based systems and embedded controller environments

Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.6

• Supports Slave Mode
• Supports Single, Dual and Quad modes
• Supports TX and RX operation as per specs
• Support for
  • Command Phase
  • Turn-Around Phase
  • Response Phase
• Baud Rate selection
• Slave Triggered Transactions
• Power management Event
• Interrupts and Alerts
• In-band reset
• Support for multiple channels
  • Peripheral channel
  • Virtual wire Channel
  • OOB Message (Tunneled SMBus) Channel
  • Run-time Flash Access Channel
• Various errors detection
• CRC Checking and generation
• The simple interface allows easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states

Available system interface wrappers:

• AMBA – APB / AHB / AXI Bus
• Altera Avalon Bus
• Xilinx OPB Bus

• Embedded Controllers (EC) in Intel CPU platforms
• FPGA and ASIC-based SoC designs requiring eSPI connectivity
• High-speed data acquisition systems and industrial peripherals
• Multi-Target microcontroller systems with low-latency communication requirements
• Replacement of legacy LPC interfaces in modern hardware architectures