Overview
The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Specification), and PIPE interface protocol (USB High-speed and Full speed). Reduced power usage is made possible by supporting extra internal power gating, reference clock control, and PLL control. Because of the versatility of the previously described low power mode choice, the PHY is also particularly beneficial for a variety of situations under different considerations of power consumption.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
