Overview
The combination PHY consists of a Serial ATA (SATA) conforming with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compatible with the PIPE interface protocol, and a USB compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed). Supporting more internal power gating, reference clock control, and PLL control results in lower power consumption. Additionally, the PHY is extensively useful for a range of circumstances under varying considerations of power consumption due to the adjustable nature of the aforementioned low power mode option.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
