Vendor: T2M GmbH Category: Single-Protocol PHY

USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP

USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication …

USB 3.1 TSMC 55nm ULP In Production View all specifications

Overview

USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. USB 3.1Type-C PHY IP is a dedicate design for USB3.1 type-C application. USB 3.1 Type C PHY IP is a pure analog IP that perform serialization and deserialization only, a dedicate PCS can be provided together with PHY to accomplish functions of different application, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. PCS is provided as either hard or soft macro based on customer’s request, the specification of PCS will also be provided separately PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.

Key features

  • Support half rate mode (5Gbps) and full rate mode (10Gbps)
  • Tolerate max +/-7000ppm input frequency offset
  • 32bit/40bit selectable parallel data bus
  • Programmable transmit amplitude
  • 3 taps/2 taps selectable FFE
  • Receiver CTLE and One-tap perspective DFE
  • Build in self-test with PRBS7/31 pattern generation and checker for production test
  • Integrated on-die termination resistors
  • Support receiver detection
  • Support LFPS signal generation and detection
  • Support Spread Spectrum clock generation and receiving
  • Flexible reference clock frequency
  • Do not need any external component
  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
  • Metal Layer:M1~M7+RDL
  • Core Voltage: 1.1V
  • IO Voltage: 3.3V
  • Silicon Proven in TSMC 55ULP.

Block Diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
TSMC 55nm ULP In Production

Specifications

Identity

Part Number
USB 3.1 Type-C PHY IP in 55ULP
Vendor
T2M GmbH
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.1

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

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Frequently asked questions about Single-Protocol PHY IP

What is USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP?

USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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