Overview
USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. USB 3.1Type-C PHY IP is a dedicate design for USB3.1 type-C application. USB 3.1 Type C PHY IP is a pure analog IP that perform serialization and deserialization only, a dedicate PCS can be provided together with PHY to accomplish functions of different application, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. PCS is provided as either hard or soft macro based on customer’s request, the specification of PCS will also be provided separately PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.
Learn more about Single-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
