Overview
The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwidth data transfers. The USB 3.1Type-C PHY IP is a particular design for USB 3.1 type-C applications. To fulfil the functionality of various applications, such as elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation checking, registers control, and testing, a separate PCS can be offered in addition to the USB 3.1 Type C PHY IP. PCS is available as a hard macro or a soft macro, depending on the customer's need. Additionally, the PCS standard will be made independently accessible. The NC-Verilog simulation program validates PHY functionality using a test bench developed in Verilog HDL.
Learn more about Single-Protocol PHY IP core
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